<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>SQRSHRN, SQRSHRN2 -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">SQRSHRN, SQRSHRN2</h2>
      <p class="aml">Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&amp;FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <a class="armarm-xref" title="Reference to Armv8 ARM section">SQSHRN</a>.</p>
      <p class="aml">The <span class="asm-code">SQRSHRN</span> instruction writes the vector to the lower half of the destination register and clears the upper half, while the <span class="asm-code">SQRSHRN2</span> instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.</p>
      <p class="aml">If saturation occurs, the cumulative saturation bit <a class="armarm-xref" title="Reference to Armv8 ARM section">FPSR</a>.QC is set.</p>
      <p class="aml">Depending on the settings in the <a class="armarm-xref" title="Reference to Armv8 ARM section">CPACR_EL1</a>, <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL2</a>, and <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL3</a> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</p>
    
    <p class="desc">
      It has encodings from 2 classes:
      <a href="#iclass_sisd">Scalar</a>
       and 
      <a href="#iclass_simd">Vector</a>
    </p>
    <h3 class="classheading"><a id="iclass_sisd"/>Scalar</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td class="r">1</td><td class="lr">0</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td>1</td><td class="r">0</td><td colspan="4" class="lr">!= 0000</td><td colspan="3" class="lr">immb</td><td class="l">1</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="lr">1</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rd</td></tr><tr class="secondrow"><td colspan="2"/><td class="droppedname">U</td><td colspan="6"/><td colspan="4" class="droppedname">immh</td><td colspan="3"/><td colspan="4"/><td class="droppedname">op</td><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="SQRSHRN_asisdshf_N"/><p class="asm-code">SQRSHRN  <a href="#sa_vb" title="Destination width specifier (field &quot;immh&quot;) [B,H,S]">&lt;Vb&gt;</a><a href="#sa_d" title="SIMD&amp;FP destination register number (field &quot;Rd&quot;)">&lt;d&gt;</a>, <a href="#sa_va" title="Source width specifier (field &quot;immh&quot;) [D,H,S]">&lt;Va&gt;</a><a href="#sa_n" title="First SIMD&amp;FP source register number (field &quot;Rn&quot;)">&lt;n&gt;</a>, #<a href="#sa_shift_1" title="Right shift amount [1-the destination operand width in bits] (field &quot;immh:immb&quot;)">&lt;shift&gt;</a></p></div><p class="pseudocode">integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);

if immh == '0000' then UNDEFINED;
if immh&lt;3&gt; == '1' then UNDEFINED;
integer esize = 8 &lt;&lt; <a href="shared_pseudocode.html#impl-shared.HighestSetBit.1" title="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(immh);
integer datasize = esize;
integer elements = 1;
integer part = 0;

integer shift = (2 * esize) - <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(immh:immb);
boolean round = (op == '1');
boolean unsigned = (U == '1');</p>
    <h3 class="classheading"><a id="iclass_simd"/>Vector</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="lr">Q</td><td class="lr">0</td><td class="l">0</td><td>1</td><td>1</td><td>1</td><td>1</td><td class="r">0</td><td colspan="4" class="lr">!= 0000</td><td colspan="3" class="lr">immb</td><td class="l">1</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="lr">1</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rd</td></tr><tr class="secondrow"><td/><td/><td class="droppedname">U</td><td colspan="6"/><td colspan="4" class="droppedname">immh</td><td colspan="3"/><td colspan="4"/><td class="droppedname">op</td><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="SQRSHRN_asimdshf_N"/><p class="asm-code">SQRSHRN<a href="#sa_2" title="Second and upper half specifier (field &quot;Q&quot;)">{2}</a>  <a href="#sa_vd" title="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a>.<a href="#sa_tb" title="Arrangement specifier (field &quot;immh:Q&quot;) [2S,4H,4S,8B,8H,16B,SEE(asimdimm)]">&lt;Tb&gt;</a>, <a href="#sa_vn" title="SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a>.<a href="#sa_ta" title="Arrangement specifier (field &quot;immh&quot;) [2D,4S,8H,SEE(asimdimm)]">&lt;Ta&gt;</a>, #<a href="#sa_shift" title="Right shift amount [1-the destination element width in bits] (field &quot;immh:immb&quot;)">&lt;shift&gt;</a></p></div><p class="pseudocode">integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);

if immh == '0000' then <a href="encodingindex.html#asimdimm" title="handled by an instruction in the 'Advanced SIMD modified immediate' class">SEE(asimdimm)</a>;
if immh&lt;3&gt; == '1' then UNDEFINED;
integer esize = 8 &lt;&lt; <a href="shared_pseudocode.html#impl-shared.HighestSetBit.1" title="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(immh);
integer datasize = 64;
integer part = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Q);
integer elements = datasize DIV esize;

integer shift = (2 * esize) - <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(immh:immb);
boolean round = (op == '1');
boolean unsigned = (U == '1');</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>2</td><td><a id="sa_2"/>
        <p>Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is 
      encoded in
      <q>Q</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">Q</th>
                <th class="symbol">2</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0</td>
                <td class="symbol">[absent]</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="symbol">[present]</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vd&gt;</td><td><a id="sa_vd"/>
        
          <p class="aml">Is the name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Tb&gt;</td><td><a id="sa_tb"/>
        <p>Is an arrangement specifier, 
      encoded in
      <q>immh:Q</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">immh</th>
                <th class="bitfield">Q</th>
                <th class="symbol">&lt;Tb&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0000</td>
                <td class="bitfield">x</td>
                <td class="symbol"><a href="encodingindex.html#asimdimm">SEE Advanced SIMD modified immediate</a></td>
              </tr>
              <tr>
                <td class="bitfield">0001</td>
                <td class="bitfield">0</td>
                <td class="symbol">8B</td>
              </tr>
              <tr>
                <td class="bitfield">0001</td>
                <td class="bitfield">1</td>
                <td class="symbol">16B</td>
              </tr>
              <tr>
                <td class="bitfield">001x</td>
                <td class="bitfield">0</td>
                <td class="symbol">4H</td>
              </tr>
              <tr>
                <td class="bitfield">001x</td>
                <td class="bitfield">1</td>
                <td class="symbol">8H</td>
              </tr>
              <tr>
                <td class="bitfield">01xx</td>
                <td class="bitfield">0</td>
                <td class="symbol">2S</td>
              </tr>
              <tr>
                <td class="bitfield">01xx</td>
                <td class="bitfield">1</td>
                <td class="symbol">4S</td>
              </tr>
              <tr>
                <td class="bitfield">1xxx</td>
                <td class="bitfield">x</td>
                <td class="symbol">RESERVED</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vn&gt;</td><td><a id="sa_vn"/>
        
          <p class="aml">Is the name of the SIMD&amp;FP source register, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Ta&gt;</td><td><a id="sa_ta"/>
        <p>Is an arrangement specifier, 
      encoded in
      <q>immh</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">immh</th>
                <th class="symbol">&lt;Ta&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0000</td>
                <td class="symbol"><a href="encodingindex.html#asimdimm">SEE Advanced SIMD modified immediate</a></td>
              </tr>
              <tr>
                <td class="bitfield">0001</td>
                <td class="symbol">8H</td>
              </tr>
              <tr>
                <td class="bitfield">001x</td>
                <td class="symbol">4S</td>
              </tr>
              <tr>
                <td class="bitfield">01xx</td>
                <td class="symbol">2D</td>
              </tr>
              <tr>
                <td class="bitfield">1xxx</td>
                <td class="symbol">RESERVED</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vb&gt;</td><td><a id="sa_vb"/>
        <p>Is the destination width specifier, 
      encoded in
      <q>immh</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">immh</th>
                <th class="symbol">&lt;Vb&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0000</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">0001</td>
                <td class="symbol">B</td>
              </tr>
              <tr>
                <td class="bitfield">001x</td>
                <td class="symbol">H</td>
              </tr>
              <tr>
                <td class="bitfield">01xx</td>
                <td class="symbol">S</td>
              </tr>
              <tr>
                <td class="bitfield">1xxx</td>
                <td class="symbol">RESERVED</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;d&gt;</td><td><a id="sa_d"/>
        
          <p class="aml">Is the number of the SIMD&amp;FP destination register, in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Va&gt;</td><td><a id="sa_va"/>
        <p>Is the source width specifier, 
      encoded in
      <q>immh</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">immh</th>
                <th class="symbol">&lt;Va&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0000</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">0001</td>
                <td class="symbol">H</td>
              </tr>
              <tr>
                <td class="bitfield">001x</td>
                <td class="symbol">S</td>
              </tr>
              <tr>
                <td class="bitfield">01xx</td>
                <td class="symbol">D</td>
              </tr>
              <tr>
                <td class="bitfield">1xxx</td>
                <td class="symbol">RESERVED</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;n&gt;</td><td><a id="sa_n"/>
        
          <p class="aml">Is the number of the first SIMD&amp;FP source register, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;shift&gt;</td><td><a id="sa_shift_1"/>
        <p>For the scalar variant: is the right shift amount, in the range 1 to the destination operand width in bits, 
      encoded in
      <q>immh:immb</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">immh</th>
                <th class="symbol">&lt;shift&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0000</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">0001</td>
                <td class="symbol">(16-UInt(immh:immb))</td>
              </tr>
              <tr>
                <td class="bitfield">001x</td>
                <td class="symbol">(32-UInt(immh:immb))</td>
              </tr>
              <tr>
                <td class="bitfield">01xx</td>
                <td class="symbol">(64-UInt(immh:immb))</td>
              </tr>
              <tr>
                <td class="bitfield">1xxx</td>
                <td class="symbol">RESERVED</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr><tr><td/><td><a id="sa_shift"/>
        <p>For the vector variant: is the right shift amount, in the range 1 to the destination element width in bits, 
      encoded in
      <q>immh:immb</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">immh</th>
                <th class="symbol">&lt;shift&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0000</td>
                <td class="symbol"><a href="encodingindex.html#asimdimm">SEE Advanced SIMD modified immediate</a></td>
              </tr>
              <tr>
                <td class="bitfield">0001</td>
                <td class="symbol">(16-UInt(immh:immb))</td>
              </tr>
              <tr>
                <td class="bitfield">001x</td>
                <td class="symbol">(32-UInt(immh:immb))</td>
              </tr>
              <tr>
                <td class="bitfield">01xx</td>
                <td class="symbol">(64-UInt(immh:immb))</td>
              </tr>
              <tr>
                <td class="bitfield">1xxx</td>
                <td class="symbol">RESERVED</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
bits(datasize*2) operand = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize*2];
bits(datasize) result;
integer element;
boolean sat;

for e = 0 to elements-1
    element = <a href="shared_pseudocode.html#impl-shared.RShr.3" title="function: integer RShr(integer value, integer shift, boolean round)">RShr</a>(<a href="shared_pseudocode.html#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned), shift, round);
    (<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a href="shared_pseudocode.html#impl-shared.SatQ.3" title="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
    if sat then FPSR.QC = '1';

<a href="shared_pseudocode.html#impl-aarch64.Vpart.write.3" title="accessor: Vpart[integer n, integer part, integer width] = bits(width) value">Vpart</a>[d, part, datasize] = result;</p>
    </div>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
    </p></body></html>
